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Micrel, Inc.
Figure 9 shows the waveforms during PW M dimming
pulses. The DRC duty cycle is 75% and th erefore the
dimming ratio (DR) is 37%. Ch1 is the switch n ode. Ch2 is
the su m of all six ILED channels. Figure 9 shows the boost
converter is OFF (not switching) between PWM dimming
pulses.
Figure 9. PWM Dimming Pulses
(Ch1 Switch Node; Ch2 is the I LED Tota l )
Direct Dimming
For direct dimming control connect DFS to V D D and use
the MODE pin for the dimming pulse. This m ethod will
bypass the internal dimming control and allows fo r
dimming control by the external PWM Dimming p ulse (see
Figure 9).
MIC3263
Figure 10. Direct Dimm ing Control
Boost Stage
A current-mode control is easi er to compensate than
voltage mode control, thus allow ing for a less complex
control loop stability design. An error amplifier amplifies
the difference between the feedback voltage and the
voltage on the CRV capacitor. This amplified error signal is
called the V CONTROL . A PWM comparator compares the
output of the error amp (V CONTROL ) to the sum of inductor
current and slope compensation currents. When the
current sums reach V CONTROL , the PWM pulse is terminated
and the boost power switch is turned off. A portion of the
energy stored in the inductor flows into the output
capacitor.
January 2010
18
M9999-012110
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